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PARAMETER
SYMBOL
CONDITIONS AND NOTES
MIN
TYP
MAX
UNIT
SCK Falling Edge to CSB Rising Edge
Setup Time
MOSI to Falling Edge of SCK Setup
Time
SCK Falling Edge to MOSI Setup Time
MOSI, CSB, SCK Signal Rise Time
MOSI, CSB, SCK Signal Fall Time
CSB Falling Edge to MISO Data Valid
CSB Rising Edge to MISO High
Impedance
t SCK:CSB(SU)
t MOSI(SU)
t MOSI(HOLD)
t R(SPI)
t F(SPI)
t CSB:MISO(DV)
t CSB:MISO(HIZ)
50
16
20
5.0
5.0
50
50
ns
ns
ns
ns
ns
ns
ns
SCK Rising Edge to MISO Data Valid
t VALID
25
80
ns
Note 1. Subject to thermal dissipation characteristics of the device
Note 2. Guaranteed by design, not production tested.
Note 3. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for
t timeout . Disable bus timeout via the Power Control register 0x02[6].
Note 4. t VD:ACK = SCL LOW to SDA (out) LOW acknowledge time.
Note 5. t VD:DAT = minimum SDA output data-valid time following SCL LOW transition.
Note 6. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state.
Note 7. The maximum SDA and SCL rise times is 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be connected
between SDA and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time.
Note 8. MSL3163/4 includes input filters on SDA, SCL, AD0 and AD1 inputs that suppress noise less than 50ns.
10
Atmel LED Drivers-MSL3163/MSL3164
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